Abstract

A novel parallel JPEG compression system based on FPGA is developed In order to enhance the efficiency of system, 8 lines of image data are buffered in the on-chip memory spaces of FPGA, which not only reduces the complexity of hardware system, but also decreases the output delay of JPEG compression. Furthermore, an image video is divided into four parts of images, and then these four parts have been compressed respectively in parallel with the base principle of JPEG compression algorithm. Through the actual test, it is concluded that the novel parallel JPEG compression system based on FPGA can process the image at the resolution of 1280^*1204 pixels with 500 frames/s real-time and efficiently.

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