An Arithmetic and Logic Unit Optimized for Area and Power
This paper presents a design of a 4-bit arithmetic logic unit (ALU) by taking vantage of the concept of gated- if fusion input (GDI) technique. ALU is the most crucial and core component of central processing unit as well as of numbers of embedded system and microprocessors. In this, ALU consists of 4x1 multiplexer, 2x1 multiplexer and fulladder designed to implements logic operations, such as AND,OR, etc. and arithmetic operations, as ADD and SUBTRACT.GDI cells are used in the design of mul- tiplexers and full adder which are then associated to re- alize ALU. The simulation iscarried out Microwind 2.0 simulator using DSCH120nm technologies and compared with previous designs realized with Pass transistor logic and CMOS logic. The simulation shows that the design is more efficient with lesspower consumption, less sur- face area and is faster as compared to pass transistor and CMOS techniques.
Author's Name: Y N S Vamsi Mohan, Nagaraju Chella and Krishnamadhav Dunnala