Abstract

Logarithmic conversion is a significant portion of numerous digital signals processing system and other applications. The antilogarithmic transformation presented in this paper is able to support the antilogarithmic conversion of data with the number of bits up to thirty-two. An efficient FPGA hardware implementation of logarithmic operations is an alternative option used in arithmetic operations. In this paper, we implemented an efficient antilogarithmic converter using FPGA. This implementation is compared with 11 and 28 regions error correction scheme. The proposed hardware architecture having less area, delay with less error cost. This design is implemented using HDL tool and synthesized using Xilinx CAD tool. The implementation has with respect to existing antilog converter.

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