High Throughput FFT System Using Baughwooley And Fused Floating Point Butterfly
A new VLSI architecture for real-time pipeline FFT processor is proposed in this project. This concept introduces a software reconfigurable OFDM system using a programmable fused-point DSP. In this project,
both radix-2 floating point butterflies are implemented more efficiently with the two fused floating-point operations. The fused operations are a two-term dot product and add-subtract unit along with Baugh-wooley multiplication algorithm. Both discrete and fused radix processors are implemented; compared in regarded with efficiency wise.
Author's Name: Korimilli Sirisha, V. Prasanna Laxmi, Dondapati Krathi Kumar