Implementation of Asynchronous Pipeline Using Verilog HDL
The asynchronous paradigm has interesting features due to the lack of the clock signal and it is another option for the project of digital systems. This paradigm has several design styles, where the micro- pipeline style is the most suitable one for FPGA platforms, due to the simplicity of its control. In this paper, we propose a pipeline architecture to implement asynchronous digital systems, in bundled-data micro- pipeline style. In this architecture we are MOUSTRAP architecture. By using this architecture we can reduce the delay as well as we can reduce the power.
Author's Name: Korimilli Sirisha, Girish Pechetti and Ramya Kudupudi