Abstract

This paper describes a generic built-in self-test strategy for devices implementing symmetric encryption algorithms. Because weak “crypto-algorithms,” poor design of the device or hardware physical failures can render the product insecure and place highly sensitive information or infrastructure at risk. Taking advantage of the inner iterative structures of crypto-cores, test facilities are easily set-up for circular self-test of the crypto-cores, built-in pseudorandom test generation and response analysis for other cores in the host device. Main advantages of the proposed test implementation are architecture with no visible scan chain, 100% fault coverage on crypto-cores with negligible area overhead, availability of pseudorandom test sources, and very low aliasing response compaction for other cores.

Paper Details