Low Power and Low Latency Modified Bist Architecture for Integrated Circuit Testing
This paper describes a low-power (LP) programmable generator producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to date built-in-self-test(BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. State of the development in the semiconductor manufacturing process, integrated chip design methodology, availability of thousand plus pin integrated circuit packaging options and efficient IC test techniques have contributed immensely towards the integration of entire system on a chip. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while the linear-feedback shift register is kept short. In both the cases, only a small number of scan chains are activated in a single cycle. Further, this project is enhanced by using bit swapping LFSR and made circuit flexible for testing both combinational and sequential circuits. Bit swapping LFSR yields less power consumption and makes efficient circuit for reliable operations.