Power Optimized FFT Architecture to Process Twin Data Streams Using Modified Booth Encoding
The primary objective of this project is to design a multi-way FFT reversal switch that has the probability of processing the paired data stream. Fast Fourier Transform (FFT) has become ubiquitous in many engineering applications. Nowadays, FFT is most widely used block in many communication and signal processing systems. This project presents a new FFT pipeline processor for the FFT calculation of two independent data streams. The FFT architecture of the multipath delay switch is used in the proposed architecture to process an N / 2 point decimation in FFT time and an N / 2 point decimation in frequency FFT operations of odd and even samples of two Data separately to reduce the area and high throughput. To achi eve the best performance of the architecture using a modified cab algorithm to minimise power.