Abstract

The VLSI circuits are prone to soft errors when they are exposed to extreme environmental conditions and there is a growing demand for low-voltage, low-power applications. The memory arrays consist of very crucial data and take enormous areas on the silicon dies. Radiation Hardening can be achieved by implementing large arrays or redundant bitcells and operated on high voltage, this adds to the overhead of area and limits the minimum operating voltage. This paper proposes high soft-error robust, low-voltage and radiation-hardened Static Random Access Memory. The proposed cell layout is only two times larger than the conventional 6T SRAM. The 13T SRAM proposed has a dual- driven separated-feedback mechanism which can tolerate high charge deposits and has low Supply Voltage. We propose Schmitt Trigger based SRAM bitcell that can operate on low supply voltages. The proposed Schmitt trigger SRAM bitcell resolves the fundamental conflicting design requirement of read versus write operation of conventional 6T bitcell and it gives better read-stability as well as better write ability compared to the other bitcell.

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